Mentor Graphics Corporation (NASDAQ: MENT) today announced its newest HyperLynx release which integrates signal and power integrity analysis, 3D-electromagnetic solving, and fast rule checking into a single unified environment. Based on the popular HyperLynx signal integrity/power integrity (SI/PI) application, this product for the first time offers designers a complete set of analysis technology sufficient for designing any type of high-speed digital printed circuit board (PCB). Spanning a wide range of underlying simulation engines and a graphical user interface (GUI) that supports both quick/interactive and exhaustive batch-mode analysis, the HyperLynx product now sets a new standard for deployment of high-speed capabilities in one easy-to-use environment.
Accurate High-Performance Simulators – All in One Environment
High-speed PCBs vary greatly in size, layer count, routing density, signaling speed, types of silicon used, and power-delivery challenges. Most tool sets offered by a single EDA vendor typically require switching applications and user interfaces for different types of analysis. By contrast, the HyperLynx tool now offers 2D/3D signal and power integrity analysis in a single application, with one GUI. Users can simulate a critical SERDES channel one minute, and then — by selecting a single new menu item — switch to analysis of a large power net’s decoupling.
Mentor has invested heavily in HyperLynx analysis technology, particularly for interconnect modeling. The product now combines a super-fast geometry extraction engine and advanced materials modeling (for wideband dielectrics, copper roughness, etc.) to produce highly accurate simulations.
Meeting the Challenges of New Technologies
SERDES technology adoption has greatly increased the frequencies used in digital signaling— even a “mainstream” protocol like PCIe Gen3 runs at 8 Gb/s. The new HyperLynx release provides advanced electromagnetic solvers, including full-wave 3D, enabling users to keep pace with increasingly fast SERDES technologies. The 3D engine is deeply integrated, so the user never has to learn the intricacies of a full-wave-solver environment. This integration ensures that signal and power structure geometries are passed; electromagnetic (EM) ports are formed; simulations are run; and S-parameter results are incorporated into time-domain simulations – automatically.
The new HyperLynx release has added multiple engines — two 2.5D solvers, the industry’s fastest DC/IR-drop simulator, and a fast quasi-static 3D solver — to enable a full set of power-integrity features, all of which are available side-by-side in the same application as the HyperLynx signal-integrity capabilities. The second, more-advanced 2.5D solver is capable of pure power and mixed signal-and-power modeling, which can be used to add accuracy to SI simulations when simultaneous-switching-noise (SSN) complications are suspected.
Streamlining Board-Wide Analysis
Simulating every detail of a PCB’s signal routing and power delivery is overwhelming. Tuning raw simulation capabilities to the specific requirements of standard interfaces and protocols (like DDRx memory and 100-Gb/s Ethernet SERDES) eases the user’s burden and provides streamlined, summary pass/fail judgment on entire interfaces. The HyperLynx wizard for DDRx memory interfaces pioneered easy setup, automated whole-bus simulation, and consolidated results reporting – and is now extended to DDR4 and LPDDR4 interfaces. HTML-based reporting allows creation of design documentation and internal Web-based “publication” of results.
In the SERDES arena, protocols that support Channel Operating Margin (COM) allow checking the quality of links based on a specific, complex set of simulation steps for a single pass/fail number per-channel. The new HyperLynx tool offers the industry’s first robust commercial implementation of COM for 100GbE signaling, with simulation details fully automated.
Staying true to its heritage of ease-of-use and fast interactive analysis, this more robust HyperLynx version can efficiently handle very large layouts (including extra-deep stack-ups, huge net counts, and entire multi-board systems); multi-processor and other simulation-engine performance enhancements; and caching and re-use of extracted models.