How do bus and board designers keep up with the increased power available from today’s computers? At Embedded Tech Trends in January, Ken Grob, director of embedded technologies at Elma Electronic, discussed what his company is doing when it comes to adaptation, including adjustments to Intel’s sixth-generation core processors.
Grob talked to me about ‘bus and board 101’ and what might be next for embedded technology. The interview with him has been split into two stories, this one and a second story that focuses on cooling.
At present, chip density is increasing, pushing the functionality of the chips forward. CPU performance is improving by 20 percent, while GPU speed increases by 50 percent in the sixth generation of Intel Processors.
Grob said that Intel particularly is working on increasing the number of graphics cores and available memory, which means that an external graphics coprocessor would not need to be added next to the CPU chip. That enables smaller form factors and increased performance, which in turn drives the overall power dissipation of the device.
The combination of CPU and GPU makes for an interesting roadmap, where multi-core processors are coupled with a local high performance graphics processing unit. “A better story is coming down the road from Intel,” Grob said. “It’s possibly necessary because of the types of things these processors are going to need to do.”
Those things include processing high resolution images and graphic rendering, such as for use in mobile devices, where images need to be able to be remapped to differently sized displays.
For Elma, the chips being more powerful means an adjustment in how some backplane architectures are built. Backplanes now have to be denser and faster, with up to 10 Gb in one lane. (They’re working toward high-speed devices in the realm of 25 Gb per second per lane, supporting 100 Gb Ethernet.)
Another change Grob sees at Elma is a need to change the way fiber is presented and packaged. He’s seeing more high quality coaxial I/O being used in backplanes, and industry standards (VITA 67.1 and similar) were adjusted to work with that. Fiber optics are also being used more often and can used to bring high speed I/O out of the chassis from the front and rear of the card.
With this comes the need to bring the fibers out to the wall of the chassis. Right now, a copper transition usually links the chip to the fiber. Grob said that in the future, card design could be changed so that transceivers are moved inside the chip, and the fiber can come out of the chip directly. Grob noted that Reflex Photonics has created a wide temperature range transceiver that can be soldered to a board, bringing optical I/O out through MT ferrules, commenting that this is highly enabling for high speed system designers.
He said that copper transitions will still probably be used for a long time, especially in general and commercial applications. Eventually, though, higher speeds will require a more direct link to the fiber.
At ETT, Grob also talked about the trend in which boxes are becoming boards as the technology changes and slims down. It’s particularly noticeable in the military, in which the amount of technology needed on a mobile platform is rapidly hitting the maximum size and weight possible in vehicle applications.
“Today their footprint for [onboard boxes] is quite large, and as capabilities or requirements change, they would add boxes to the vehicles,” Grob said. “This becomes cumbersome and drives weight and space. Ultimately it drives power, as there is only so much to go around. Ultimately, they run out of space for other things, such as space for soldiers to operate the equipment! Converging these systems, by consolidating boxes into boards, can provide some additional elbow room.
Therefore, things need to be made smaller. In order to do that, different types of devices can be merged into a common chassis. A box level function can now be done on a board. System-on-chip systems are trending toward very large logic footprints supporting very high speed transceivers. This isn’t entirely new, but Grob said that he’s seeing “a big effort” to do it more often now, and to enable it by working within new standards such as OpenVPX.
The conversation between standards makers and manufacturers is always ongoing. With all of the changes happening in the fundamental architecture and the methods needed to cool it, the way military platforms are implemented appears to be moving to a converged approach that drives SWaP-C reduction.
Filed Under: Rapid prototyping
