Synopsys Enters Embedded Memory Market

MOUNTAIN VIEW, Calif. and ALISO VIEJO, Calif.– Synopsys, Inc. (NASDAQ: SNPS) and Novelics announce the expansion of Synopsys' DesignWare® IP portfolio with the addition of an innovative SRAM-1T embedded memory IP that is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs. As part of a cooperative technology licensing and development relationship with Novelics, Synopsys will also offer a family of low-power and high-performance standard SRAM IP. The new silicon-proven DesignWare embedded memory IP will enable the design and manufacturing of higher performance and more power-efficient system-on-chips (SoCs).

DesignWare coolSRAM-1T™ Memory IP

Content and feature-rich products require faster, more power-efficient SoCs with increasingly large amounts of on-chip memory. High-density SRAM-1T memory IP enables integration of up to three times more memory than a standard 6T-SRAM, enabling chips to incorporate more system memory on-chip, thus lowering power and overall system cost. The DesignWare coolSRAM-1T is implemented on a bulk logic CMOS process and does not require additional masks or manufacturing steps. This implementation provides designers with a true zero-added-cost solution, offering up to 15 percent reduction in manufacturing costs compared to existing SRAM-1T products.

Unlike competitive solutions, the DesignWare coolSRAM-1T memory IP is a compiler-based solution providing designers with immediate access to the specific memory IP instance they need without any compromise on instance storage capacity or topology. The combination of not having to pay a premium on wafer price coupled with the flexibility of the compiler-based technology enables designers to reduce system-level power and cost, even for designs with small amounts of memory.

DesignWare coolSRAM Memory IP

In addition to the SRAM-1T offering, Synopsys will provide a family of high-performance and low-power standard SRAMs that include single port 6T, dual port 8T, register file and ultra high density ROM. The new DesignWare coolSRAM memory IP enables the implementation of a 32Kb Cache memory operating well over 1GHz while drawing less than 6uW/MHz as measured on a leading 65nm low-power process. The compilers also include advanced power control features such as leakage control and block-level sleep mode to implement system-level power management, enabling increased battery life for portable devices.

Availability

The SRAM and SRAM 1T IP will be available in the first quarter of 2008. For more information on the DesignWare Embedded Memory IP, visit http://www.synopsys.com/embedded_memory.

Synopsys
www.synopsys.com

Novelics
www.novelics.com

::Design World::