By Deisgn World Staff
MOUNTAIN VIEW, Calif. — Synopsys, Inc. (NASDAQ: SNPS), announces the availability of the industry’s first concurrent hierarchical design system as part of the IC Compiler 2007.12 release. The IC Compiler 2007.12 enables a concurrent methodology where planning occurs in tandem with implementation, delivering faster time to tapeout. The 2007.12 release also introduces new advances in clock tree synthesis technology that improves clock skew and lowers power dissipation. The new release directly boosts designer productivity by providing a 30 percent reduction in total run time.
IC Compiler 2007.12 provides hand-craft-quality macro placement, intelligent power network support, and MinChip technology for automatic die-size reduction, all on a single timer foundation that enables faster time to closure with higher quality of results (QoR). This flow is differentiated by a high degree of automation combined with high-quality optimization.
Prominent among core-technology advances in the 2007.12 release are optimization improvements which maintain IC Compiler’s QoR advantage while slashing total runtime by 30 percent, as validated across a broad range of 65-nanometer (nm) customer designs. IC Compiler 2007.12 introduces unique advances in clock tree synthesis, such as an innovative new clustering algorithm which delivers 20 percent reduction in clock buffering area to improve routing congestion as well as power dissipation. In addition, new skew optimization enables improved timing closure for challenging designs, and an integrated clock-gate merging capability delivers another five to ten percent reduction in clock tree power.
Filed Under: Semiconductor manufacture, ENGINEERING SOFTWARE